1. Field of the Invention
The present invention relates to an integrated circuit device having an input circuit for loading input signals from outside using input load timing signals generated by a self timing control circuit based on an external clock, and more particularly to an integrated circuit device which disables loading of input signals by a timing signal while phase adjustment has not ended at a power on or at return from a power down so as to prevent an internal malfunction.
2. Description of the Related Art
A known example of an integrated circuit device which operates internal circuits synchronizing with clocks supplied from outside is a synchronous DRAM (SDRAM). Such a synchronous integrated circuit device loads input signals and outputs output signals synchronizing with external clocks. In the case of a conventional integrated circuit device, an input signal from outside, such as a command signal, is loaded to an input circuit directly using clock signals supplied from outside as the input loading timing signals.
Recently, to improve the data transfer speed of semiconductor devices, the frequency of clock signals is becoming quite high. Because of this trend, the time from loading a clock signal into a chip until the clock signal is used as a timing signal tends to vary due to the impact of various conditions, such as temperature and power supply voltage. This decreases the allowable time to load an input signal, making it extremely difficult to implement a sufficient operation margin.
A method proposed to solve this problem is generating the input loading timing signal CLK2 synchronizing with the external clock signal CLK using a DLL (Delay Locked Loop) circuit, which is a self timing control circuit, and loading an input signal synchronizing with the input loading timing signal CLK2. This configuration is stated in Japanese Patent Laid-Open No. 10-112182 (disclosed on Apr. 28, 1998).
FIG. 1 is a drawing depicting a configuration example of a conventional self timing control circuit and an input circuit. An external clock CLK is supplied to DLL circuit circuit 2 as a reference clock CLK 1 via a clock input buffer 1. The DLL circuit circuit 2, which is comprised of a later mentioned phase comparison circuit, a delay control circuit, a dummy input buffer, and a variable delay circuit, generates an input loading timing signal CLK 2 synchronizing with the external clock signal CLK, and supplies it to an input buffer 4 in the input circuit 3.
Command signals from outside, that is, a row address strobe signal /RAS, column address stroke signal /CAS, chip select signal ICS and write enable signal /WE are supplied to the input buffer 4. The input buffer 4 loads the command signals and transfers then to a command decoder 5 synchronizing with the input loading timing signal CLK 2. The command decoder 5 generates a control signal based on the loaded command signals, and supplies it to the internal circuits.
The DLL circuit circuit 2 adjusts the phase of the input loading timing signal CLK2 so as to match or enter a predetermined phase relationship with the phase of the external clock CLK. The input signal from outside is then loaded synchronizing with the external clock CLK by using the phase adjusted input loading timing signal CLK2. While the DLL circuit circuit 2 is in the phase adjustment stage, however, the phrase of the input loading timing signal CLK2 to be generated does not match with the phase of the external clock CLK, and if an input command is loaded synchronizing with such an input loading timing signal CLK2 whose phase is not adjusted, an incorrect input command may be loaded, which causes a malfunction of internal circuits. Also an incorrect address signal may be loaded, which causes access to an incorrect address.
A phase adjustment period is, for example, when power is turned on or when returning from a power saving operation (power down operation). When power is turned on, phase is adjusted after the delay of the internal variable delay circuit is reset to the initial state, as is mentioned later. Therefore, during the phase adjustment period, the phase difference between the external clock signal CLK and the input loading timing signal CLK2 increases. Also in a standby mode of the power saving operating, such as self refresh mode or power down mode, where power consumption is decreased, operation of the DLL circuit is stopped by the stop in loading the external clock CLK, or clock frequency is decreased or power supply voltage is decreased even if the DLL circuit continuously operates. As a result, the delay of the variable delay circuit of the DLL circuit greatly deviates from the delay which is set in a normal operation. Therefore, after returning from standby mode, the phase difference between the external clock signal CLK and the input loading timing signal CLK2 is large.
At the moment, in a predetermined period after power is turned on or after returning from standby mode, the product catalog states that input of a command signal is forbidden at setup time and hold time based on the external clock signal CLK. This prevents a malfunction of the internal circuits caused by loading an incorrect command signal and address signal.
However, if the phase adjustment of the DLL circuit has not ended when the above mentioned predetermined time has elapsed at power on or after returning from standby mode, an input signal may be loaded at incorrect timing, and the above mentioned forbidden input, stated in the product catalog, cannot completely prevent a malfunction of the integrated circuit device. Also, in a period other than power on or after returning from standby mode, the phase of the input loading timing signal CLK2 generated by the DLL circuit may greatly deviate from the external clock CLK due to such cause as a power supply noise. In such a case, an input command signal or an address signal may be loaded at a timing that is greatly deviated from the timing of the external clock CLK, which causes a malfunction of the internal circuits as well.